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SGT - Next Generation Semiconductor

The Surrounding Gate Transistor or SGT, has the unique three-dimensional structure in which all three electrodes of source, gate and drain are placed in the vertical plane with the gate electrode surrounding a silicon column. On the contrary, the conventional MOS transistors have the planar device structures where source, gate and drain are located in the horizontal plane. The planar MOS transistors have improved the device performance and reduced the production costs at the same time by scaling device size. However, this scaling technology of planar transistors is expected to reach its limitation within a decade. To overcome the scaling limitation, SGT technology was invented by Dr. Masuoka in 1988. This novel structure:

 
  • significantly reduces the space required for each individual transistor.

  • is expected to reduce power consumption.

  • is expected to have lower production costs.

  • will produce greater than 10 times processing speeds.

  • With this innovative SGT structure, the clock frequency of microprocessors will be boosted to 20GHz, a full order of magnitude greater than the current 2GHz planar MOS transistor. It is believed that the technology is capable of operating at clock speeds of 50 GHz or more. Our current research focuses on designing new SGT structure with the device simulator to achieve the high density and high performance devices. We also fabricate the actual SGT devices and integrated circuits to evaluate the device characteristics. Our aim is acquiring the powerful patents that will lead the future nanoelectronic technology.


    Comparison between a Traditional MOS Transistor and the SGT


    Inverter circuit

            Figure1 Click to view.

    MOS transistors are planar devices with a silicon substrate (or base material) in which the individual elements of the transistor are formed by discrete layers of material (Figure 1).

    An insulating oxide layer is deposited over the top of the substrate, and may also be used to form a gate region. Source and drain regions are formed on either side of the gate region by doping the silicon substrate with a material with a large excess of electrons.

    The region below the gate and directly between the source and drain regions, is known as the channel. Although the source and drain regions are identical, convention has defined the source as the electrical node with the lower of the two voltage potentials at either end of the channel. When a voltage is applied to the gate, the size of the channel can be controlled, thus also controlling the conduction of electrons across the channel between the source and drain.


    Inverter circuit using SGT technology

            Figure2 Click to view.

    The SGT is characterized by the vertical placement of the electrodes, source, gate and drain (Figure 2). An n-type diffusion region, an oxide film, and metallic plate are formed in layers around a silicon pole to give the SGT it's unique column construction. This construction reduces the area of the substrate occupied by each discrete component (i.e. each transistor) by 30% when compared with traditional MOS transistors. The SGT operates in a similar manner to the conventional MOSFET. A voltage applied to the gate controls the size, channel and consequently also controls the conduction of electrons across the channel between the source and drain.


    The Benefit of the SGT


    Inverter circuit using conventional MOS technology

            Figure3 Click to view.

    Using the SGT the "footprint" or area of the substrate occupied by each discrete component (i.e. transistor) is reduced. A typical inverter circuit formed using SGT technology would occupy 1/8 less area than an equivalent inverter circuit using MOSFET technology if the gate, source and drain regions had similar dimensions (i.e. a reduction of 12.5%). This can be illustrated with reference to the drawings above where an inverter circuit using conventional NPN MOS transistor is shown on the left, an SGT transistor is shown in the middle, and the layout of an inverter circuit using SGT transistors is shown on the right.

       
       
     
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